Priority is claimed from Republic of Korean patent application No. 99-62961 filed Dec. 27, 1999, which is incorporated in its entirety by reference.
1. Field of the Invention
The invention relates generally to a method of manufacturing a capacitor in a semiconductor device. More particularly, the present invention relates to a method of manufacturing a capacitor in a semiconductor device that can prevent soft error, maintain a stable operation and has a good leakage current characteristic in a DRAM.
2. Description of the Prior Art
A manufacturing technology for a semiconductor device necessarily involves research on improving the performances of a transistor and a capacitor. Particularly, in order to prevent soft error and maintain a stable operation in a DRAM, a capacitance of more than 25fF per unit cell is required and the leakage current must be sufficiently low. As a dielectric such as the existing Si3N4/SiO2 (NO) or Ta2O5 has an insufficient dielectric constant, however, research into a high dielectric such as SrTiO3 and (Ba, Sr) TiO3 (Barium Strontium Titanate; hereinafter called xe2x80x9cBSTxe2x80x9d) has been actively progressed as a capacitor having a high dielectric constant in Giga DRAM. At the same time, research into an underlying electrode for a storage node also has been actively progressed.
A conventional method of manufacturing a capacitor using high dielectric constant consisted of material thin films such as SrTiO3 and BST having high dielectric constant will be explained by reference to FIGS. 1 and 2.
FIG. 1 is a cross-sectional view of a device for explaining a method of manufacturing a capacitor in a semiconductor device according to a first conventional method.
As shown, a first interlayer insulating film 12 and a second interlayer insulating film 13 are sequentially formed on a substrate 11 in which an underlying structure is formed. Then, for a vertical wiring of the substrate 11 and a capacitor, a selected region of the second and first interlayer insulating films 13 and 12 are etched to form a contact hole. Next, the contact hole is buried with polysilicon and is flatten to form a capacitor plug 14. Thereafter, a contact layer 15 and a diffusion prevention film 16 are formed on the entire structure. After an underlying material is formed on the diffusion prevention film 16, the underlying electrode material, the diffusion prevention film 16 and the contact layer 15 are patterned to form an underlying electrode 17. Next, a dielectric film 18 and an upper electrode 19 are formed on the entire structure using BST, thereby completing manufacturing a capacitor.
However, in the above mentioned method, as the design rule of a semiconductor device is smaller, angle of more than 80xc2x0 must be maintained at a given height of the underlying electrode 17. However, there is a problem that angle of a given degree could not be maintained due to difficulty in a process etching. Also, when the dielectric film 18 is formed, there is a problem that the contact layer 15 and the diffusion prevention film 16 at the side surface of the underlying electrode are exposed.
FIG. 2 is a cross-sectional view of a device for explaining a method of manufacturing a capacitor in a semiconductor device according to a second conventional method.
As shown, after a first interlayer insulating film 22 and a second interlayer insulating film 23 are sequentially formed on a semiconductor substrate 21 in which an underlying structure is formed, for a vertical wiring of the substrate 21 and a capacitor, a selected region of the second and first interlayer insulating film 23 and 22 are etched to form a contact hole. Then, after a polysilicon layer is formed so that the contact hole can be buried to a certain depth, a contact layer 25 and a diffusion prevention film 26 are formed on the polysilicon layer and are then flatten. Thus, the internal of the contact hole is buried with a capacitor plug 24 by the polysilicon layer, the contact layer 25 formed on the capacitor plug 24, and the diffusion prevention film 26. Next, after an underlying electrode material is formed on the entire structure and is then patterned to form an underlying electrode 27, a dielectric film 28 and an upper electrode 29 are formed on the entire structure using BST, thereby completing manufacturing a capacitor.
As such, in the method of manufacturing a capacitor according to the second conventional method, when the dielectric film 28 is formed, in order to prevent from exposing the contact layer 25 and the metal/oxygen diffusion prevention film 26, there has been attempted that the contact layer 25 and the diffusion prevention film 26 are formed in a plug shape so that they are located only inside the contact hole. However, it is impossible to avoid a misalignment between the bottom electrode mask and the contact mask and therefore the diffusion prevention film plug is exposed. Therefore, there is a problem that the characteristic of leakage current after the BST dielectric film is formed is degraded.
It is therefore an object of the present invention to provide a method of manufacturing a capacitor in a semiconductor device, by which an underlying electrode can be formed to a desired height without a process of etching an underlying electrode wherein the process has a difficulty in manufacturing a stack-type capacitor using BST, and therefore a misalignment between a capacitor plug and an underlying electrode that can be generated upon etching of the underlying electrode can be prevented and directly contacting a metal/oxygen diffusion prevention film with a dielectric film are avoid, thereby preventing diffusion of oxygen when a dielectric film is formed.
In order to accomplish the above object, a method of manufacturing a capacitor in a semiconductor device according to the present invention is characterized in that it comprises the steps of forming a first interlayer insulating film on a semiconductor substrate in which an underlying structure is formed, etching a portion of the first interlayer insulating film in which a capacitor will be formed, and forming a first contact hole; forming a polysilicon layer on the entire structure including the first contact hole and then etching the polysilicon layer; sequentially forming an adhesive layer and a diffusion prevention film on the polysilicon layer and then flattening them to bury the first contact hole; sequentially forming a second interlayer insulating film and an O3-PSG film on the entire structure in which a diffusion prevention film is formed and then removing a selection region of the O3-PSG film and the second interlayer insulating film to form a second contact hole; forming an underlying electrode material on the entire structure in which the second contact hole is formed, sequentially removing the underlying electrode material on the O3-PSG film and said O3-PSG film, thereby completing an underlying electrode; and sequentially forming a dielectric film and an upper electrode on the entire structure in which the underlying electrode is formed.